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Code No. Project Title Base Paper Abstract Video
VL83 Design of Optimized Reversible Binary and BCD Adders(IEEE 2015) Download Download
VL84 Design of Priority Encoding Based Reversible Comparators(IEEE 2015) Download Download
VL85 Energy and Area Efficient ThreeInput XOR XNORs With Systametic Cell Design Methodology(IEEE 2015) Download Download
VL86 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels(IEEE 2015) Download Download
VL87 High Speed Modified Bulk stimulated Ultra Low Voltage Domino Inverter(IEEE 2015) Download Download
VL88 IC Layout Design of Decoder Using Electric VLSI Design(IEEE 2015) Download Download
VL89 Implementation of high performance SRAM Cell Using Transmission Gate(IEEE 2015) Download Download
VL90 Implementation of Testable Reversible Sequential Circuit on FPGA(IEEE 2015) Download Download
VL91 Index based Round Robin Arbiter for NoC Routers(IEEE 2015) Download Download
VL92 Logic Debugging of Arithmetic Circuits(IEEE 2015) Download Download
VL93 Low-Complexity Tree Architecture for Finding the First Two Minima(IEEE 2015) Download Download
VL94 Low-Power and Area-Efficient Shift Register Using Pulsed Latches(IEEE 2015) Download Download
VL95 Modeling CMOS Gates Using Equivalent Inverters(IEEE 2015) Download Download
VL96 On the Analysis of Reversible Booth’s Multiplier(IEEE 2015) Download Download
VL97 Online Testing for Three Fault Models in Reversible Circuits(IEEE 2015) Download Download
VL98 Parallel Prefix Modulo Adder via Double Representation of Residues in [0, 2](IEEE 2015) Download Download
VL99 Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers(IEEE 2015) Download Download
VL100 Quantum Cost Realization of New Reversible Gates with Transformation Based Synthesis Technique(IEEE 2015) Download Download
VL101 Recursive Approach to the Design of a Parallel Self-Timed Adder(IEEE 2015) Download Download
VL102 Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm(IEEE 2015) Download Download
VL103 Reversible Logic Based Mapping of Quaternary Sequential Circuits(IEEE 2015) Download Download
VL104 Synthesis of Balanced Quaternary Reversible Logic Circuit(IEEE 2015) Download Download
VL105 Towards reversible QCA computers reversible gates and ALU(IEEE 2015) Download Download
VL106 Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits(IEEE 2015) Download Download
VL107 Variable Latency Speculative Han-Carlson Adder(IEEE 2015) Download Download
VL108 Ultralow-Energy Variation-Aware Design Adder Architecture Study(IEEE 2015) Download Download
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