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Code No. Project Title Base Paper Payment Video
VL01 Design Of 16-Bit Multiplier Using Modified Gate Diffusion Input Logic(IEEE 2019) Download Buy
VL02 Low power 4×4 bit multiplier design using dadda Algorithm and optimized full adder (IEEE 2019) Download Buy
VL03 Dlau: a scalable deep learning accelerator unit On fpga (IEEE 2019) Download Buy
VL04 Design of low-power high-performance 2–4 and 4–16 mixed-logic line decoders IEEE 2019) Download Buy
VL05 Design and implementation of 32-bits mips Processor to perform qrd based on fpga (IEEE 2019) Download Buy
VL06 True Single-Phase Adiabatic Circuitry(IEEE 2019) Download Buy
VL07 A Modified Partial Product Generator for Redundant Binary Multipliers IEEE 2019) Download Buy
VL08 A Deep Reinforcement Learning Network for Traffic Light Cycle Control (IEEE 2019) Download Buy
VL09 Design and Analysis of Carry Look Ahead Adder Using CMOS Technique (IEEE 2019) Download Buy
VL10 Design and Analysis of Carry Look Ahead Adder Using CMOS Technique (IEEE 2019) Download Buy
VL11 Low-Power, High-Sensitivity Readout Integrated Circuit With Clock-Gating (IEEE 2019) Download Buy
VL12 Supply Voltage Dependency on the Single Event(IEEE 2019) Download Buy
VL13 High Speed Low Power Flash ADC Design for Ultra Wide Band Applications(IEEE 2019) Download Buy
VL14 A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications (IEEE 2019) Download Buy
VL15 Ultra-Low Power Platform Applications (IEEE 2019) Download Buy
VL16 "Material analysis of high degree of variability in thin CMOS for SRAM current sense amplifier" (IEEE 2019) Download Buy
VL17 "Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction" (IEEE 2019) Download Buy
VL18 Low Power BIST based Multiplier Design and Simulation using FPGA (IEEE 2019) Download Buy
VL19 Optimizing the Implementation of SEC–DAEC Codes in FPGAs (IEEE 2019) Download Buy
VL20 A Low Latency and Resource Efficeient Enable RSA Cryptoprocessor Architecture (IEEE 2019) Download Buy
VL21 Design and Analysis of Digital Counters for VLSI Applications (IEEE 2019) Download Buy
VL22 VLSI Implementation of Turbo Coder for LTE using Verilog HDL (IEEE 2019) Download Buy
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