Enquiry

VLSI Projects      Contact:9789339435 ; 9500580005

Code No. Project Title Base Paper Abstract Video
VL01 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator(IEEE 2016) Download Download
VL02 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units (IEEE 2016) Download Download
VL03 A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T BitCell Enabling Logic-in-Memory (IEEE 2016) Download Download
VL04 A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes (IEEE 2016) Download Download
VL05 A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost (IEEE 2016) Download Download
VL06 An Efficient Approach to Design a Compact Reversible Programmable Logic Array (IEEE 2016) Download Download
VL07 Design for Testability of Sleep Convention Logic (IEEE 2016) Download Download
VL08 Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder (IEEE 2016) Download Download
VL09 Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders (IEEE 2016) Download Download
VL10 Design of Register File using Reversible Logic (IEEE 2016) Download Download
VL11 Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method (IEEE 2016) Download Download
VL12 Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model (IEEE 2016) Download Download
VL13 Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking (IEEE 2016) Download Download
VL14 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation(IEEE 2016) Download Download
VL15 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels(IEEE 2016) Download Download
VL16 Logic Synthesis in Reversible PLA (IEEE 2016) Download Download
VL17 Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion Input Method (IEEE 2016) Download Download
VL18 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing(IEEE 2016) Download Download
VL19 Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA (IEEE 2016) Download Download
VL20 Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions (IEEE 2016) Download Download
VL21 Modeling of Adders using CMOS and GDI Logic for Multiplier Applications (IEEE 2016) Download Download
VL22 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding(IEEE 2016) Download Download
VL23 Primitive components of Reversible Logic Synthesis (IEEE 2016) Download Download
VL24 Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits (IEEE 2016) Download Download
VL25 Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs (IEEE 2016) Download Download
VL26 Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3- D Multicore Processors (IEEE 2016) Download Download
VL27 Design Methodology for Voltage-Scaled Clock Distribution Networks (IEEE 2016) Download Download
VL28 A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications (IEEE 2016) Download Download
VL29 5-bit 5-GS/s Non interleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications M (IEEE 2016) Download Download
VL30 A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme (IEEE 2016) Download Download
VL31 A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring (IEEE 2016) Download Download
VL32 A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current Mode Controlled Switching Regulators (IEEE 2016) Download Download
1  |  2  |  3
Call us : 9789339435 / 9500580005
Mail ID : finalyearprojects@s3techindia.com