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Code No. Project Title Base Paper Abstract Video
VL01 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging(IEEE 2017) Download Download
VL02 Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture (IEEE 2017) Download Download
VL03 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding(IEEE 2017) Download Download
VL04 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption (IEEE 2017) Download Download
VL05 Resource-Efficient SRAM-based Ternary Content Addressable Memory (IEEE 2017) Download Download
VL06 Write-Amount-Aware Management Policies for STT-RAM Caches (IEEE 2017) Download Download
VL07 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA (IEEE 2017) Download Download
VL08 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder (IEEE 2017) Download Download
VL09 High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations (IEEE 2017) Download Download
VL10 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST (IEEE 2017) Download Download
VL11 Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map (IEEE 2017) Download Download
VL12 Efficient Designs of Multi-ported Memory on FPGA (IEEE 2017) Download Download
VL13 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA (IEEE 2017) Download Download
VL14 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock (IEEE 2017) Download Download
VL15 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique (IEEE 2017) Download Download
VL16 Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares (IEEE 2017) Download Download
VL17 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm (IEEE 2017) Download Download
VL18 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission (IEEE 2017) Download Download
VL19 Scalable Device Array for Statistical Characterization of BTI-Related Parameters (IEEE 2017) Download Download
VL20 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding (IEEE 2017) Download Download
VL21 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware (IEEE 2017) Download Download
VL22 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs (IEEE 2017) Download Download
VL23 Efficient Soft Cancelation Decoder Architectures for Polar Codes (IEEE 2017) Download Download
VL24 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition (IEEE 2017) Download Download
VL25 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication (IEEE 2017) Download Download
VL26 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers (IEEE 2017) Download Download
VL27 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields (IEEE 2017) Download Download
VL28 Antiwear Leveling Design for SSDs With Hybrid ECC Capability (IEEE 2017) Download Download
VL29 Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems (IEEE 2017) Download Download
VL30 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding (IEEE 2017) Download Download
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